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IP Name(IP名称)	IP Description(IP描述)	IP Owner(IP提供商)
BusBridge™ 2 Module	No delay in MBB2 module except when demanded by one of the bus protocols or timing considerations. CPU Core system interface (Note: Where a description applies to both the EC? and OCP interfaces this document will use the term CoreIF.) Supports all Core
FUSBH100	USB 1.1 host controller with AHB interface.
EP440	PCI-to-PCI Bridge
Amphion CS5230	AES EncryptionFast
CC400	SPI 4.2 Interface
KLP25G	0.25u Non Volatile Memory (Prog ROM / FLASH alternative) with Standard Logic CMOS processes
UAPC-5110	DMA Controller Lite
Tricore1	32-bit DSP/MCU/MPU core
PL031	Real Time Clock (RTC)
FTSMC020	Static memory controller with AHB interface.
Sigma-Delta ADC/DAC Converters	Sigma-Delta ADC/DAC Converters
10 Gbps Ethernet FIFO Memory Interface	Supports IEEE802.3x Full Duplex Provides data queuing for increased system level throughput User-definable storage sizes I/O ports independent of clock speed Single or multiple word data transfer Programmable high and low receive storage level indica
QCPCIEX1-13T	Quad 3.1Gsps SerDes TRX
BQ-PCI32-01 64/32-bit PCI v2.2 Target Core	PCI stands for Peripheral Component Interconnect.
MAP03T	Very High Speed 8 State MAP Decoder
CS326D	The CS326D is a member of the C*Core 32-bit RISC core family, designed specifically for secure System on Chip (SoC) applications, which combine China’s Guomiban (国密办) software, manufacturer’s secure boot-code and customer/user’s Operating System (O/S) and
JS24Z121	IEEE802.15.4 Single Chip
TCI-T13G-DDRLDLL	TSMC CL013G 0.13um DDR DLL - 51MHz-255MHz
TL6108FS	0.2GHz/250MSPS Dual Frequency Synthesizer
CM-SI-ME-000	Montgomery Exponentiator Co-processor
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