| CSC |
Color Space Convertor |
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| CWda01 |
The CWda01 is an SPDIF-AES/EBU receiver which extracts audio data and clock information by
sampling the input signal with a fast clock signal unrelated to the sample rate frequency. |
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| Libra-Visa 0.25-micron Chartered Library |
0.25-micron Chartered Library |
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| E1/T1/J1 Framer Core Multi-channel |
Aliathon’s E1/T1/J1 Framer core provides a flexible, resource-efficient, programmable-logic based solution for level 1 PDH interfacing. |
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| RDDES |
DES and Triple DES data encryption / decryption |
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| BA114 |
JPEG 2000 Compatible Inverse Wavelet Transform |
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| HC68901 |
68901 / 68HC901 Core |
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| XAP2 |
16-bit ASIC processor |
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| USB-HS SPH / MPH |
USB 2.0 High Speed Single Port Host (SPH) and Multi Port Host (MPH) controller IP Cores |
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| CI12318cg |
USB2.0 PHY LS-FS-HS 3.3-1.8-1.8 UTMI+ |
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| BA115 |
High Speed Baseline DCT-JPEG Color Decoder |
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| SPCUSB20 |
USB 2.0 Device IP Core |
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| 9-bit Low Power ADC |
Very low power operation
Fully differential design
Power down mode
Continuous conversion mode for maximum conversion rate and successive-conversion mode for additional control
Modular design to facilitate customization and process migration |
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| UPLL-0006-250 |
0.25um 500MHz PLL-Based Clock Generator |
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| VA08V 64/256 State Viterbi Decoder |
. 64 or 256 state (constraint length 7 or 9) Viterbi
decoder
. Up to 222 MHz internal clock
. Rate 1/2, 1/3, or 1/4 (inputs can be punctured for
higher rates)
. 4–bit received signed magnitude data
. Optional block decoding with or without tail |
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| AFM8101a |
Low Voltage Power-Line MODEM with 283 uVRMS |
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USB Generic Function Controller |
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PCI to PCI Bridge |
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| MOSAID® DDR/DDR2 SDRAM PHY |
Compatible with JEDEC standard DDR2 and DDR SDRAMs
Supports data rates of 800Mb/s and beyond
Confi gurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
Permits operating with DDR/DDR2 SDRAMs using data widths narrower tha |
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| CellMath |
CellMath application libraries offer improvements for your graphics acceleration and high performance processor design |
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