| cclasic/generic/bias/1.0 |
Generic bias circuit |
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| ViaMask |
A Via Programmed Structured ASIC Technology |
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| TCI-T13LVOD-LBLPLL |
TSMC CL013LVOD 0.13um Low Banwidth PLL |
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| M4VENH |
MPEG4 Video Output Enhancement Processor |
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IMT-2000 3GPP Turbo Codec |
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| TTIVID01-V11/98 |
Viterbi Decoder |
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| T-CA-PL-0022-100-UU18 |
220 to 330 MHz (FREF 24.576 to 30 MHz) 1.8V PLL |
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Artisan 0.13um Voltage Regulator for TSMC |
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| sha1_md5_compact_xilinx |
Secure Digital SD/MMC/IO Host Controller Interface |
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| LD-ATA-0014-050 |
Servo Interface |
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| QCLVDS3-13T |
Low Voltage Differential Signaling (LVDS) Transceiver, 1.244 GHz, 1.2v/3.3v Pads using 1.2V/3.3V FSG process. |
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| DW_sqrt |
Combinational Square Root |
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| FXPORA010HC0H |
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA; HS process with A-type I/O.; Power On Reset; UMC 0.13um Logic HS (FSG) process |
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| DivX_MSVD |
DivX Multi Standard Video Decoder (MPEG-1, MPEG-2, MPEG-4 ASP, DivX 5.x, XviD) |
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| CW000701_2_1 |
DDR PHY |
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| PCI Arbiter |
Conforms to PCI Local Bus Specification revision 2.2,Supports up to 8 PCI master devices,Supplies Hidden Bus Arbitration |
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| DW03_lfsr_load |
LFSR Counter with Loadable Input |
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| IP-RSDEC |
Reed-Solomon Compiler, Decoder |
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| fp-divideunit |
? IEEE-like Arithmetic
(Denormals treated as
Zeros)
? IEEE Single Precision
Format
? Fully Synchronous Design
? All outputs registered
? Minimal combinational logic
on inputs
? 15-clock pipeline rate
? 17-clock latency |
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| PLL48 |
PLL, Input 8~24MHz, output 12~48MHz |
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