面向对象：正在进行数字IC 设计的工程师及工程管理人员
时间：2008年5月19 星期一& 5月20日星期二 （9：30-18：00）
地点：深圳集成电路设计产业化基地管理中心培训教室
地址：深圳市高新中区科技中二路软件园一期四号楼六层

Workshop Description:
In this workshop, we will review the major low power techniques including multi-supply multiple-voltage, power shut-off, and biasing techniques. It will cover CPF modeling and authoring techniques which can be used to drive the whole timing closure  flow including implementation, analysis, and sign-off. How to handle each low power specific IPs, for example, level-shifters, isolation cells, power switches, always-on buffers, state-retention cells, well-tapping cells and well-separation issues, are also covered. Labs are included to exercise what we’ve learned in the class and the whole SOCE low power flow can be tried and tested using a small demo case in this workshop 

Speaker Introduction:
The speakers are very experienced R&Ds, who work on low power projects on a daily basis:
    - Pinhong Chen, R&D Director of Low Power and CTS for SOCE
    - Kunming Ho, Senior Member of Consulting Staff, Low Power R&D

Agenda
5月19日 星期一 （Aenda –Day 1）
    9:00-9:30 Registration
    9:30-11:00  Low power design overview
    11:00-16:00  Common Power Format (CPF) 
        Power domain basics
        CPF authoring and development -basic 
        Lunch (Cadence provide) 
        Lab1– CPF creation and  debugging 
        CPF authoring and development-MMMC and DVFS  
        Lab2 - CPF creation and verification (MMMC and DVFS)
    16:00-16:20  SOCE Low Power Flow 
    16:20– 18:00Initialization and setup
        Load CPF
        Adjust power domains
        Low power verification
        PSO
        Lab3 – PSO
5月20日 星期二 （Agenda- Day 2）

    9:00-9:30　　Registration
    9:30-14:30　　Pre CTS flow 
        Placement (shifter/isolation placement)
        Lab 4: power domain shaping and shifter/isolation placement
        Power planning and power routing
        Secondary power/ground routing
        Power domain aware optimization
        Always on nets handling  
    12:00-13:00 Lunch
        Lab 5: secondary power/ground routing and bufferTreeSynthesis
        Power domain aware routing
        Lab 6 - debugging using CLP  
    14:30 -14:50　　PostCTS and post route flow
    power domain aware CTS
    pulsed-latch
    Leakage power optimization  
    14:50 -15:40   Sign Off flow
        Voltage Storm Interface (Common Power Engine, Sign-Off Rail analysis,Decap optimization)
        Multiple-supply multiple-voltage in timing analysis flow   
15:40 -17:30 Hierarchical and IP-reuse flow
        CPF hierarchical flow: top-down hierarchical flow, hierarchical CPF, bottom-up hierarchical flow
        Lab 7 – Hierarchical CPF  

在线注册
    http://www.cadence.com/events/cn/china_registration/index.aspx?event_id=36&event_code=sz

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