课程时间：2天(11月27-28日)
培训地点：SZICC培训教室
培训地址：深圳市科技园中区软件园4栋615教室
主讲老师：Synopsys 公司资深工程师
培训费用： 400元/人（包括工作午餐、教材、实验费用等）

Workshop Goal
Acquire the skills to verify and debug Verilog designs using Synopsys VCS

Workshop Measurable Objectives
By the end of this workshop you should be able to:
        Simulate Verilog designs using VCS
        Debug Verilog designs using VCS
        Run fast RTL-level regression tests for your Verilog design
        Run fast gate-level regression tests for your Verilog design
        Acquire the skills and knowledge to successfully implement coverage driven verification methodology using Synopsys tools

Agenda:
Day 1:
        VCS Simulation Basics
        VCS Debugging Basics
        Debugging with DVE
        Post-Processing with VCD+ Files
Day 2:
        Debugging Simulation Mismatches
        Fast RTL Level Verification
        Fast Gate Level Verification
        Code Coverage

附：培训报名表