中心资源
      技术及认证培训
      学历教育
      专题讲座及研讨会
      联系我们

首页 > 培训中心 > 技术与认证培训

Virtuoso XL Layout Editor 培训

主办单位:国家集成电路深圳产业化基地
承办单位: Cadence Shenzhen Office


课程简介:
Virtuoso-XL Layout Editor是Cadence 功能强大交互式的全定制数字和模拟IC版图编辑器。新型的强大的命令集同先进的版图编辑技术相结合,使其支持纯多边形、参数化单元、符号化版图与压缩、版图综合等多种输入方法,快速的设计层次浏览以及多窗口环境使用户同时编辑多个设计。该培训课程,学员将利用典型设计案例学习原理图或网表驱动式的集成电路版图设计技术。

举办时间:2005年3月9日-11日(三天)
报名地点:深圳高新技术园南区深港产学研基地大楼东座E208室
主讲教师:Cadence资深工程师
培训费用:非协议企业 ¥ 1500.00/人; 自费个人 ¥ 1200.00/人; 服务签约企业 ¥ 900.00/人
(包括工作午餐、教材费、上机实验费)

课程目标:
· Set the environment for the Virtuoso XL Layout Editor
· Generate a layout from a schematic
· Edit a placed design
· Create interconnect manually
· Create interconnect using the Wire Editor
· Abstract your designs with the Abstract Generator
· Floorplan your design with Virtuoso Preview
· Route your design with the Virtuoso Chip Assembly Router
· Analyze and update your design
· Set up and complete a hierarchical design
· Place your design with Virtuoso Custom Placer

课程大纲:
Day 1
Introduction to Virtuoso XL Layout Editor
Virtuoso XL setup
Layout generation
Editing Virtuoso XL placement
Creating interconnect in Virtuoso XL

Day 2
Creating interconnect with the Wire Editor
Generating abstracts
Floorplanning with Virtuoso Preview
Routing with Virtuoso Chip Assembly Router
Analyzing and updating data

Day 3
Working with hierarchical designs and variables
Virtuoso Custom Placer setup
Pin placement using Virtuoso Custom Placer
Placement styles and automatic placement

适合人员:
· Library Developers
· ASIC Designers
· Chip Designers
· Design Engineers
· Layout Designers
· Digital IC Designers
· Analog/Mixed-Signal IC Designers
· IC Designers
· Developers who create and route designs for analog or digital ICs

课程要求:
Prerequisites: You need experience with: Virtuoso Layout Editor, Cell Design Tutorial;
You should already have knowledge of: Layout Experience, CMOS Devices, UNIX OS

期望准备
You are encouraged to complete the Cell Design Tutorial before taking this course. The Cell Design Tutorial comes with the software as part of the documentation package. The data for the tutorial is part of the Cadence installation hierarchy.

The path to the tutorial data is:
<dfII_install_path>/etc/samples/tutorials/le/cell_design

联络人:周岩 电话:0755-26984896 E-MAIL:

附:培训报名表





 
  国家集成电路设计深圳产业化基地管理中心 深圳市高新技术产业园区中区科技中二路软件园一期四号楼六楼
电话:0755-86168939 86168684 传真:0755-86168949 Email:Center@szicc.net