Allegro PCB SI Foundations
Description:
This course teaches you how to use the Allegro PCB SI tool to successfully develop and drive design rules for high-speed designs.
You learn to develop high-speed design rules using Allegro PCB SI XL and then add the resulting physical and electrical constraints to the design through topology templates. These constraints are then used to drive the routing of nets on the printed circuit board.
You perform pre-route and post-route signal simulations to analyze the PCB for reflection, simultaneous switching, crosstalk, and other high-speed design factors.
Learning Objectives:
In this course you will learn to:
- Create, extract, and explore topologies.
- Execute Solution Space Analysis.
- Create an Electrical Constraint Set.
- Use constraints to drive placement and routing.
- Run post-route DRC check.
- Use template revision to update the ECSet applied on the nets/bus.
- Analyze the routed board design for Signal Integrity.
- Create a DesignLink between boards and use it to run multi-board simulation.
Audience:
- PCB Layout Designers
- PCB Designers
- Electrical Engineers
举办时间： 2007年7月23日-25日（3天）
报名地点：科技园中区科技中二路软件园4栋6楼615教室
主讲教师： Cadence公司资深工程师
培训费用： RMB 600.00/人 （包括工作午餐、教材费、实验费等）
联系人：周岩 电话：0755-86168846 email: zhouy@szicc.net
Course Agenda
Day 1
- Allegro PCB SI Design Flow
- Basic Features of Allegro PCB SI XL
- Board Setup Requirements
- Database Setup Advisor
- Signal Models and Library Browser
- Creating DesignLink
- Initializing System Configuration
- Setup for Topology Extraction
- Unrouted Topology Extraction
- Allegro PCB SI XL Simulation
- Delay Measurements
- Allegro PCB SI XL Simulation Directory Structure
Day 2
- What is Solution Space Analysis
- Appending Topologies
- Creating Custom Measurements
- Assigning Strobe and Data Pins in Source Synchronous Design
- Parametric Sweeps
- Assigning Constraints in a Topology Template
- Building a Topology
- Coupled Trace Models
- Crosstalk Simulation in SigXplorer
- Key Features of the Constraint Manager
- Allegro PCB SI Constraints
- ECSet Application to a Bus
- Physical and Electrical Constraints
- Performing Timing-Driven Placement
- Analyzing in the Constraint Manager
Day 3
- Updating a Topology
- Performing a DRC Audit
- Signal Analysis
- SigNoise Report Generation
- Performing Post-Route Simulations in Allegro PCB SI
- Extracting and Viewing a Routed Xnet Topology
- Differential Pair Net Extraction and Analysis
Constraint-Driven Routing of Differential Pair Nets
附:参会回执
