* This course is flow-based. It draws heavily on Tcl commands to implement the design.
* In this course, you will execute all the major steps required to complete the design flow from gate level through place and route.
* You will fix signal integrity and timing problems using parasitic data extracted with the Fire & Ice extractor.
* You will run power analysis and view the IR drop in your design.
Course Objectives
In this course, you will
* Explore high-level and hierarchical design planning and virtual prototyping.
* Run Amoeba and block placement.
* Route the design with Trial Route.
* Estimate parasitics and run delay calculation.
* Create clock trees.
* Run delay calculation.
* Optimize timing.
* Run final route.
* Extract parasitics.
* Run crosstalk analysis.
* Run power analysis.
举办时间： 2008年1月14日—15日（2天）
报名地点：科技园中区科技中二路软件园4栋621
主讲教师： Cadence公司资深工程师
培训费用： RMB 400.00/人 （包括工作午餐、教材费、实验费）
Course Agenda
?Day 1
* Introduction to the SoC Encounter Environment
* Logic Synthesis
* Silicon Virtual Prototyping
* Flat Chip Implementation
* Hierarchical Budgeting and Partitioning
Day 2
* Detailed Block Implementation
* Top-Level Implementation
* Chip Assembly and Validation
* Timing and Signal Integrity Closure
* Premask ECO Flow
* Postmask ECO Flow
联系人：周岩 0755-86168846 zhouy@szicc.net
附：培训报名表
