举办时间：2005年 12月27日—12月28日（2天）
上课地点：深圳市科技园南区深港产学研基地大楼东座E207室
上课时间：9:30 AM – 5:30 PM
主讲教师： Synopsys公司资深工程师
联络人 ： 王懿小姐 电话: 82070122-103 传真: 82070133 email: jojowang@synopsys.com


OVERVIEW
This two-day workshop covers, via lecture and lab, the basics of formal verification.
On the first day, students will apply a formal verification flow for:
       Verifying a design
       Debugging a failed design
On the second day, students will apply an extended flow in order to:
       Optimize Formality for common hardware design transformations
       Increase debugging capability through techniques such as pattern analysis
       Maximize verification performance


OBJECTIVES
At the end of this workshop the student should be able to:
       Describe where Formality fits in the design flow
       Read a reference design and the libraries for that design into Formality
       Read a revised design and the libraries for that design into Formality
       Set up for verification interactively and with scripts
       Handle common design transformations for easiest verification
       Guide Formality in matching names between two designs
       Verify that two designs are equivalent
       Debug designs proven not to be equivalent
       Optimize reads, compare point matching and verification


AUDIENCE PROFILE
Design or Verification engineers who understand traditional functional verification methods, and who want to perform verification more quickly, without using vectors.
PREREQUISITES
Knowledge of digital logic.
COURSE OUTLINE

Day 1
       Introduction
       Controlling Formality
       Setting up and running Formality
       Debugging designs proved not equivalent
Day 2
       Design transformations and their effect on equivalence checking
       Advanced debugging
       Maximizing performance


SYNOPSYS TOOLS USED
Formality 2002.05