举办时间：2005年 5月31日—6月2日（3天）
上课地点：深圳市科技园南区深港产学研基地大楼东座E207室
上课时间：9:30 AM – 5:30 PM
主讲教师： Synopsys公司资深工程师
联络人 ： 王懿小姐 电话: 82070122-103 传真: 82070133
email: jojowang@synopsys.com
因名额有限, 欲报从速, 请以Synopsys 最后确认通知为准
OVERVIEW
In this intensive, three-day course, you will
learn the key features and benefits of the OpenVera
hardware verification language and its use in
Vera or VCS NTB.
This course is a hands-on workshop that re-enforces
the verification concepts taught in lecture through
a series of intense labs. At the end of this class,
students should have the skills required to write
an object-oriented OpenVera testbench to verify
a device under test with coverage-driven random
stimulus using Vera or VCS NTB.
Students will first learn how to develop an interface
between OpenVera testbenches and their Device
Under Test (DUT). Next the workshop will explain
how the intuitive object-oriented technology in
OpenVera can simplify verification problems. This
course concludes with an in-depth discussion of
functional coverage including a uniform, measurable
definition of functionality and the Vera constructs
that allow you to assess the percentage of functionality
covered either dynamically or through the use
of generated reports.
To reinforce the lecture and accelerate mastery
of the material, each student will complete a
challenging test suite for real-world, system-based
design.
OBJECTIVES
At the end of this workshop the student should
be able to:
* Build an OpenVera verification environment
* Develop stimulus generators to create constrained
random test data
* Develop device driver routines to drive DUT
input with stimulus
* Develop device monitor routines to sample DUT
output
* Develop self-check routines to verify operation
of DUT
* Abstract DUT hardware signals as software variables
* Abstract DUT data as objects
* Execute device driver, monitor and self-checking
routines concurrently
* Communicate among concurrent routines using
sync/trigger, semaphore and Smart Queues
* Develop functional coverage to measure completeness
of test
AUDIENCE PROFILE
Design or Verification engineers who write testbenches
at the block or chip level
PREREQUISITES
To benefit the most from the material presented
in this workshop, you should have:
* An understanding of basic concepts of design
verification
* Experience with a high-level programming language
(such as C) and with an HDL (such as Verilog)
* Familiarity with UNIX workstations running X-windows
* Familiarity with vi, emacs or other UNIX text
editor
COURSE OUTLINE
Day 1
* Introduction
* The Device Under Test
* OpenVera Verification Environment
* OpenVera Language Basics
* Driving and Sampling DUT Signals
* Virtual Ports
Day 2
* Concurrency
* Object Oriented Programming: Encapsulation
* Object Oriented Programming: Randomization
Day 3
* Inter-Thread Communication
* Object Oriented Programming: Inheritance
* Functional Coverage
SYNOPSYS TOOLS USED
VCS 7.2
Vera 6.3.30
附：报名回执表
