举办时间：2006年 11月28日(星期二)—11月30日(星期四)（3天）
上课地点：深圳集成电路设计产业化基地: 深圳市高新区中区科技中二路软件园一期四号楼6楼培训室(
见地图)
上课时间：9:30 AM – 5:30 PM
主讲教师： Synopsys公司资深工程师
联络人 ： 荆滔先生 电话: 82070122-102, 13510093703 传真: 82070133 email: tjing@synopsys.com
注：1、请以Synopsys确认通知为准
2、请自带纸笔。
System Verilog Testbench
OVERVIEW
In this intensive, three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS.
This course is a hands-on workshop that reinforces the verification concepts taught in lecture through a series of labs. At the end of this class, students should have the skills required to write an object-oriented SystemVerilog testbench to verify a device under test with coverage-driven random stimulus using VCS.
Students will first learn how to develop an interface between the SystemVerilog test program and the Device Under Test (DUT). Next the workshop will explain how the intuitive object-oriented technology in SystemVerilog testbench can simplify verification problems. This course concludes with an in-depth discussion of functional coverage including a uniform, measurable definition of functionality and the SystemVerilog constructs that allow you to assess the percentage of functionality covered either dynamically or through the use of generated reports.
To reinforce the lecture and accelerate mastery of the material, each student will complete a challenging test suite for real-world, system-based design.
AUDIENCE PROFILE
Design or Verification engineers who write testbenches at the block or chip level
PREREQUISITES
To benefit the most from the material presented in this workshop, you should have:
* An understanding of basic concepts of design verification
* Working knowledge of Verilog
* Experience with a high-level programming language (such as C)
* Familiarity with UNIX workstations running X-windows
* Familiarity with vi, emacs or other UNIX text editor
COURSE OUTLINE
Day 1
* Introduction
* The Device Under Test
* SystemVerilog Verification Environment
* SystemVerilog Testbench Language Basics
Day 2
* Managing Concurrency in SystemVerilog
* Object Oriented Programming: Encapsulation
* Object Oriented Programming: Randomization
Day 3
* Object Oriented Programming: Inheritance
* Functional Coverage
SYNOPSYS TOOLS USED
附：报名回执表
