OVERVIEW
In this workshop you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. The workshop will show you how to analyze the reported data to identify common DFT violations and then fix the original RTL design.
The workshop explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length and reusing functional pins for scan testing; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to reduce the number of ATPG patterns required for a given fault coverage.
OBJECTIVES
At the end of this workshop the student should be able to:
* Define the test protocol for a design and customize the initialization sequence, if needed
* Perform DFT checks at both the RTL and gate-levels
* State common design constructs that cause typical DFT violations
* Automatically correct certain DFT violations at the gate-level using AutoFix.
* Insert scan to achieve well-balanced top-level scan chains and other scan design requirements
* Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and Place & Route.
* Implement Rapid Scan Synthesis (RSS) in a top-down scan insertion flow achieving well-balanced scan chains
* Modify a bottom-up scan insertion script for full gate-level designs to use Test Models/ILMs with RSS and run it
* Preview top-level chain balance using test models/ILMs after block-level scan insertion and revise block level * scan architecture as needed to improve top level scan chain balance.
* Insert additional observe test points to reduce number of ATPG patterns.
AUDIENCE PROFILE
ASIC or SoC Design and Test engineers who need to check for, identify and fix design-for-test violations in their RTL or gate-level designs, insert scan into possibly multi-million gate ASICs, and export design files to ATPG and Place&Route tools.
PREREQUISITES
There are no prerequisites for this workshop. Prior experience with Design Compiler, Design Vision and writing Synopsys TCL scripts is useful, but not required.
COURSE
OUTLINE
Day 1
* Understanding Scan Testing
* DFTC User Interfaces
* Creating Test Protocols
* DFT for Clocks and Resets
Day 2
* DFT for Buses/Tristates
* Top-Down Scan Insertion
* Exporting Design Files
* High Capacity DFT Flows
Day 3
* New Features
* DFT MAX
* Clock Gating
* Conclusion
SYNOPSYS TOOLS USED
* DFT Compiler 2006.06 XG Mode
* Design Vision 2006.06 XG Mode
* Design Compiler 2006.06 XG Mode
* TetraMAX 2006.06
附：报名回执表
