Verification with VCS
￠ Overview
This two-day workshop introduces the student to Verilog design verification using VCS with a focus on debugging techniques, verification performance and coverage driven verification environment implementation. This course is mixed lecture and exercises, with exercises for both RTL and gate-level verifications. All major features of VCS, compiler, debugger, simulator, Coverage Metrics and utilities are covered.
￠ Objectives
At the end of this workshop, the student should be able to:
· Compile Verilog designs using VCS
· Simulate Verilog designs using VCS
· Debug Verilog source code errors using VCS
· Debug Verilog simulation mismatches using VCS utilities
· Determine simulation bottlenecks with VCS utilities
· Run fast RTL-level Verilog regression tests using VCS
· Run fast gate-level Verilog regression tests using VCS
· Collect code coverage and implement coverage driven verification methodology using VCS
￠ Prerequisite
· Understanding of digital IC design
· Familiarity with UNIX and X-Windows
· Familiarity with a UNIX-based text editor
· Familiarity with Verilog
￠ Course Outline
· VCS simulation basics
· VCS debugging basics
· Debugging with DVE
· Post-Processing with VCD+ Files
· Debugging simulation mismatches
· Fast RTL level verification
· Fast Gate Level verification
· Code Coverage
￠ Synopsys Tools Used
VCS
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