举办时间：2007年4月10-12日星期二-四（3天）
上课地点：深圳集成电路设计产业化基地: 深圳市高新区中区科技中二路软件园一期四号楼6楼615培训室
上课时间：9:30 AM – 5:30 PM
主讲教师： Synopsys公司资深工程师
联络人 ： 王懿小姐 电话: 82070122-60480 传真: 82070133 email: jojowang@synopsys.com
注：1、请以Synopsys确认通知为准 2、请自带纸笔。

OVERVIEW
The workshop starts out with a high level introduction to IC Compiler’s graphical user interface, during which you will learn about the 3 core commands, place_opt, clock_opt and route_opt as well as the more targeted atomic commands for more specific needs.

You will learn the details of design and timing setup, including setting up all physical and logical libraries, importing various design formats and floorplans, and setting the design up for proper timing analysis.

The workshop goes in-depth into using IC Compiler to perform placement, power optimization, scan optimization, clock tree synthesis and routing operations, including interleaved logic optimizations. You will also learn how to perform Design for Manufacturing tasks in IC Compiler, including antenna fixing, via doubling, metal filling and critical area optimization.

Another unit is dedicated to the topic of the new Multi Scenario capabilities, including how to apply SDC constraint files and operating conditions and perform analysis and optimization in parallel. The unit will also show you the advantages of using on-chip variation mode.

The class will explore the new Design Planning features in IC Compiler, which support full flat floorplanning including automatic macro placement, power network synthesis and analysis, and prototype route and optimization.

The workshop is accompanied by comprehensive hands-on labs, which provide an opportunity to apply all concepts covered during the lectures.

OBJECTIVES
At the end of this workshop you should be able to:
* Read necessary files required to run IC Compiler, resolving common errors/warnings
* Set up timing for analysis and optimizations
* Perform placement and optimizations
* Analyze congestion maps and reports
* Perform power optimization
* Perform scan reordering using ScanDEF
* Set up the design for clock tree synthesis
* Perform clock tree synthesis and post CTS optimizations
* Analyze timing and clock specifications post CTS
* Route the design using the core and atomic commands
* Describe the need for Multi-corner, Multi-Mode analysis and optimization
* Specify a scenario in IC Compiler
* Analyze the design for SI and perform SI optimizations
* Perform unconstrained and freeze silicon ECOs
* Perform antenna fixing, via doubling, metal filling, filler cell insertion, critical area optimization
* Create a flat floorplan including core and IO area setup, power network synthesis and routing, timing driven macro placement
* Perform power network analysis and virtual pad insertion

AUDIENCE PROFILE
ASIC, back-end or layout designers with experience in standard cell-based automatic Place and Route.

PREREQUISITES
To benefit the most from the material presented in this workshop, students should have working knowledge of Physical Design using Physical Compiler, Astro, or any other Physical Design tool.

COURSE OUTLINE
Day 1
* Introduction
* IC Compiler Basic Flow
* Placement, Power andTest
Day 2
* Clock Tree Synthesis
* Multi Scenario Optimization
Day 3
* Design Planning
* Routing and Signal Integrity
* Chip Finishing and DFM

SYNOPSYS TOOLS USED
* IC Compiler 2006.06