举办时间：2007年10月30-31日星期二－三（2天）
上课地点：深圳集成电路设计产业化基地: 深圳市高新区中区科技中二路软件园一期四号楼6楼615培训室
上课时间：9:30 AM – 5:30 PM
主讲教师： Synopsys公司资深工程师
培训费用： RMB750/人/天 （包括教材和午餐）,共1500元
联络人 ： 请填写附件报名表，传真或者email给：王懿小姐 电话: 82519830， 13823126282 传真: 82519801 email: jojowang@synopsys.com
注：请以Synopsys确认通知为准

Power Compiler

OVERVIEW
This course introduces the uses of Power Compiler and RTL Power Estimator. You will learn to link Power PLI tasks with the VCS simulator, perform pre-synthesis power estimates using several techniques, and perform both RTL and gate-level power analysis and optimization.

OBJECTIVES
At the end of this class, the student should be able to:
* Link the Power PLI using VCS
* Generate switching activity files from simulation
* Generate power estimates in RTL Power Estimator and identify power-hungry design blocks
* Use clock gating and operand isolation techniques in Power Compiler to reduce power consumption
* Generate and examine power reports in Power Compiler
* Use gate-level power optimization for further power reduction

AUDIENCE PROFILE
Design engineers who want an introduction to power estimation, analysis, and optimization with Power Compiler and RTL Power Estimator.

PREREQUISITES
To benefit the most from the material presented in this workshop, students should:
* Understand Verilog and/or VHDL
* Be able to use a Verilog or VHDL simulator
* Be familiar with UNIX workstations running X-windows
* Be familiar with Design Compiler
* Be familiar with vi, emacs, or another UNIX text editor

COURSE OUTLINE
Day 1
* Power libraries
* RTL power estimation
* RTL switching activity
* RTL Optimization (Clock Gating and Operand Isolation)
Day 2
* RTL Optimization (cont)
* Gate level power analysis and optimization
* Leakage Power and Dual Vt

附：培训报名表