举办时间：2006年 7月12日—7月13日（2天）(星期三-星期四)
上课地点：深圳市高新区中区科技中二路软件园一期四号楼6楼培训室
上课时间：9:30 AM – 5:30 PM
主讲教师：Synopsys公司资深工程师
联络人 ： 王懿小姐 电话: 82070122-103 传真: 82070133
email: jojowang@synopsys.com
因名额有限, 欲报从速, 请以Synopsys 最后确认通知为准
、请自带纸笔。
Outline
Day1: Hsim basic training
1) Hsim technology
2) Hsim 101 (Lab)
3) Setting Hsim parameters (Lab)
4) Hsim speed/accuracy tradeoff adjustment (Lab)
5) Hsim DC analysis (Lab)
6) Interactive debugging (Lab)
7) Misc. Features
Day2: Hsim advance training
1) Postlayout simulation flow (Lab)
2) Power net /Signal net MOSFET reliability analysis (Lab)
3) Co-simulation setup
Hsim Platform Overview
Full-chip Hierarchical Circuit Simulation & Analysis
HSIMplus platform is for the comprehensive simulation and analysis of high performance analog, mixed-signal, memory, and system-on-chip designs including important post-layout effects.
HSIM Technology
HSIM incorporates four unique and proprietary technologies which deliver the breakthrough levels of simulation performance and memory efficiency required for full-chip nanometer circuit verification, while maintaining SPICE levels of precision.
* Hierarchical Circuit Database. This hierarchical approach to circuit storage efficiently represents repeated instances of the same sub-circuit and provides almost unlimited design capacity.
* Hierarchical Simulation Engine. HSIM isomorphic matching technology takes advantage of any hierarchical structures present in the circuit, eliminating unnecessary simulation and accelerating performance. HSIM offers the latest simulation models including BSIM4 for MOS devices, VBIC for bipolar devices, and BSIMSOI3 for silicon-on-insulator devices.
* Nanometer Problems Solver. HSIM proprietary methods for circuit representation are uniquely capable of handling circuits with inductors and coupling capacitors. By controlling the impact of these parasitics on the numerical solver, the simulation of parasitic effects causes only a minor slow down.
* Proprietary Parasitic Reduction Algorithms. HSIM simulation core implements a state-of-the-art RC parasitic reduction capability. This reduction effectively reduces the huge volume of parasitic data associated with layout parasitic extraction, boosting performance for efficient post-layout simulation with a negligible loss in accuracy.
附：报名回执表
深圳集成电路设计产业化基地地图
