举办时间：2008年2月28-29日 星期四到星期五
上课地点：深圳集成电路设计产业化基地: 深圳市高新区中区科技中二路软件园一期四号楼6楼615培训室
上课时间：9:30 AM – 5:30 PM
培训费用： RMB750/人/天 （包括教材和午餐）,共1500元
联络人 ： 请填写附件报名表，传真或者email给：王懿小姐 电话: 82519830， 13823126282 传真: 82519801 email: jojowang@synopsys.com
注：请以Synopsys确认通知为准


SystemVerilog Verification Using VMM Methodology

OVERVIEW
In this hands-on workshop, you will learn how to develop a Verification Methodology Manual (VMM) environment structure which can implement any SystemVerilog test with minimal modification. Within this VMM environment structure, you will develop stimulus factories, check and coverage callbacks, message loggers, transactor managers, and data flow managers. Once the VMM environment has been created, you will learn how to easily add extensions for more test cases.
After completing the course, you should have developed the skills to write a coverage-driven random stimulus based VMM testbench that is robust, re-useable and easy to maintain.

OBJECTIVES
At the end of the course you should be able to:
* Develop an VMM environment class in SystemVerilog
* Implement and manage message loggers for printing to terminal or file
* Build a random stimulus generation factory
* Build and manage stimulus transaction channels
* Build and manage stimulus transactors
* Implement checkers using VMM callback methods
* Implement functional coverage using VMM callback methods

AUDIENCE PROFILE
Design or Verification engineers who develop testbenches using SystermVerilog VMM base classes.

PREREQUISITES
To benefit the most from the material presented in this workshop, students should:
Have taken the SystemVerilog Testbench workshop
OR
Possess equivalent knowledge of SystemVerilog testbench including:
* Creating/Using SystemVerilog interfaces
* How to encapsulate testbench components in SystemVerilog class structure
* Familiarity with SystemVerilog class inheritance
* Creating/Using System Verilog queues
* Creating Cover Group for functional coverage

COURSE OUTLINE
Day 1
* OOP inheritance review
* The VMM Environment
* VMM Message Service
* VMM data model
* Stimulus Generator/Factory
Day 2
* Check & Coverage (Callbacks)
* Transactor Implementation
* Data Flow Control (Broadcast/Scheduler)
* Scenario Generator
* Methodology Recommendations

SYNOPSYS TOOLS USED
VCS 2006.06-SP1

附：培训报名表