举办时间：2008年8月7-8日 星期四到星期五
上课地点：深圳集成电路设计产业化基地: 深圳市高新区中区科技中二路软件园一期四号楼6楼615培训室
上课时间：9:30 AM – 5:30 PM
培训费用： RMB700/人/天 （包括教材和午餐）,共1400元
联络人 ： 请填写附件报名表，传真或者email给：王懿小姐 电话: 82519830， 13823126282 传真: 82519801 email: jojowang@synopsys.com
注：请以Synopsys确认通知为准
Formality
OVERVIEW
This course covers the ASIC formal verification flow using Formality. In this course, you can learn what’s Formality and where it fits in your design flow? Furthermore, Some advanced usage and debugging experience will be introduced to you. The course includes labs to reinforce and practice key topics discussed in lecture.
OBJECTIVES
At the end of this workshop the student should be able to:
Describe the seven-step Formality flow
Create and run a script to compare two designs
Save the results of a verification for later analysis
Use command line declaration of Verilog Text Macros to match either VCS or DC
List 4 ways of creating a blackbox model
List the three categories of causes for simulation/synthesis differences
Explain the benefits of using the Synopsys Guidance Flow (SVF files) in matching compare points
List and explain the 7 point types that appear in Formality’s summary report for a verification
Explain how valid design transformations can cause a failing verification
Apply the recommended debugging procedure to a failing verification
Describe some potential causes of false failures when verifying a design hierarchically
AUDIENCE PROFILE
ASIC digital designers who are going to use Formality to do formal verification.
PREREQUISITES
To benefit the most from the material presented in this workshop, you should:
Understand the functionality of digital sequential and combinational logic
Have familiarity with UNIX and a UNIX text editor of your choice
No prior Formality knowledge or experience is needed
COURSE OUTLINE
Day 1
Introduction to Formality
Getting Started with Formality
Basic Formality Flow
Reading Designs
Matching
Verification
Day 2
Advanced Setup – Design Transforms
Debug
Advanced Usage
附：培训报名表
