举办时间：2008年8月28-29日 星期四到星期五
上课地点：深圳集成电路设计产业化基地: 深圳市高新区中区科技中二路软件园一期四号楼6楼615培训室
上课时间：9:30 AM – 5:30 PM
培训费用： RMB700/人/天 （包括教材和午餐）,共1400元
联络人 ： 请填写附件报名表，传真或者email给：王懿小姐 电话: 82519830， 13823126282 传真: 82519801 email: jojowang@synopsys.com
注：请以Synopsys确认通知为准

Star-RCXT

OVERVIEW
In this workshop, students will learn the fundamentals of RC extraction using Star-RCXT. Students will start by creating a technology process file, which will be used by Star-RCXT for extraction, including setting up all of the required files: i.e., process file, layer mapping file, command file, runset (Hercules), rule deck and query file (Calibre). Next, students will perform RC extraction on the gate-level (using Milkyway, LEF/DEF flows), and transistor-level designs (using Hercules and Calibre flows). Depending on the application, the output parasitic netlist can be generated in one of the required formats: DSPF, SPEF, SBPF and so on; students can retain the coupling capacitances separately.
Students will also be shown how to debug databases that have problems such as shorts and opens. For accuracy checking, students will perform capacitance correlation of Star-RCXT results with 3D field solver reference results. Practical issues such as selective netlisting, metal fill and non-planar process support will also be discussed.
Students will apply the concepts during the labs following each lecture.

OBJECTIVES
At the end of this workshop the student should be able to:
        Describe the fundamentals of extraction (top-down and hierarchical)
        Write a process file starting from the specifications and a template
        List the flows of Star-RCXT in RC extraction
        Set up & perform cell (gate) -level extraction using Milkyway and LEF/DEF flows
        Specify the requirements for selective netlisting
        Describe the requirements for a transistor-level extraction
        Set up & perform transistor level extraction using the Hercules or Calibre flow
        Choose a required back annotation mode (XREF) while generating the
        parasitic netlist
        Correlate the capacitance accuracy and extract selected nets using a 3D field solver
        Perform extraction with real and emulated metal fills
        Model non-planar conductors for legacy processes

AUDIENCE PROFILE
Backend designers, or process technologists who use Star-RCXT to perform extraction for sign off. Verification Engineers who perform sign-off static timing analysis using a parasitic RC back-annotation flow.

PREREQUISITES
To get the most out of this workshop, the following are suggested, but not required:
        Familiarity with place & route tools
        Familiarity with transistor-level tools & flows
        Familiarity with physical design verification tools
        Familiarity with parasitic back annotation for static timing analysis

COURSE OUTLINE
Day 1: Cell (Gate) -level extraction
        Extraction fundamentals
        Process modeling
        Gate-level extraction flows
        Selective netlisting
Day 2: Transistor-level extraction
        Transistor-level extraction flows
        Back annotation modes (XREF)
        Capacitance correlation and accuracy
        Metal fill and non-planar process support
        Conclusion

附：培训报名表