举办时间：2008年9月17-19日 星期三到星期五
上课地点：深圳集成电路设计产业化基地: 深圳市高新区中区科技中二路软件园一期四号楼6楼615培训室
上课时间：9:30 AM – 5:30 PM
培训费用： RMB700/人/天 （包括教材和午餐）,共2100元
联络人 ： 请填写附件报名表，传真或者email给：王懿小姐 电话: 82519830， 13823126282 传真: 82519801 email: jojowang@synopsys.com
注：请以Synopsys确认通知为准

Design Compiler 1

OVERVIEW
This course covers the ASIC synthesis flow using Design Compiler -- from reading in an RTL design (Verilog and VHDL) to generating a final gate-level netlist. You will learn how to read in your design file(s), specify your libraries, constrain a complex design for area and timing, partition your design’s hierarchy for synthesis, apply synthesis techniques to achieve area and timing closure, analyze the synthesis results, and generate output data that works with downstream layout tools. The course includes labs to reinforce and practice key topics discussed in lecture. All the covered commands and flows are printed separately in a 3-page Job Aid which the student can refer to back at work.

OBJECTIVES
At the end of this workshop the student should be able to:
        Create a setup file to specify the libraries that will be used
        Read in a hierarchical design
        Partition a design’s hierarchy optimally for synthesis
        Constrain a complex design for area and timing, taking into account different environmental attributes such as output loading, input drive strength, process, voltage and temperature variations, as well as post-layout effects such as clock skew and net parasiticsy
        Select the appropriate compile flow for your project
        Execute the recommended synthesis techniques within each compile flow to achieve area and timing closures
        Perform test-ready synthesis when appropriate
        Write DC-Tcl scripts to constrain and compile designs
        Generate and interpret timing, constraints and other debugging reports
        Understand the effect that RTL coding style can have on synthesis results
        Generate output data (netlist, timing/are constraints, physical constraints scan-def) that works with downstream physical design or layout tools

AUDIENCE PROFILE
ASIC digital designers who are going to use Design Compiler to synthesize Verilog or VHDL RTL modules to generate gate-level netlists.

PREREQUISITES
To benefit the most from the material presented in this workshop, you should:
        Understand the functionality of digital sequential and combinational logic
        Have familiarity with UNIX and a UNIX text editor of your choice
        No prior Design Compiler knowledge or experience is needed

COURSE OUTLINE
Day 1
        Introduction to Synthesis
        Setting Up and Saving Designs
        Design and Library Objects
        Partitioning for Synthesis
        Area and Timing Constraints
Day 2
        Environmental Attributes
        Compile Commands
        Timing Analysis
        More Constraint Considerations
        Multiple Clock/Cycle Designs (Lecture)
Day 3
        Multiple Clock/Cycle Designs (Lab)
        Synthesis techniques and Flows
        Integrated Design-for-Test
        Pre- and Post-Synthesis Considerations
        Conclusion

SYNOPSYS TOOLS USED
Design Compiler 2007.03

附：培训报名表