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IP Name(IP名称) IP Description(IP描述) IP Owner(IP提供商)
Cortex-M0 处理器 ARM Cortex?-M0 处理器是目前最小的 ARM 处理器。该处理器的芯片面积非常小,能耗极低,且编程所需的代码占用量很少,这就使得开发人员可以直接跳过16位系统,以 接近8 位系统的成本开销获取 32 位系统的性能。Cortex-M0 处理器超低的门数开销,使得它可以用在在模拟和数模混合设备中。 ARM
DW02_mac Multiplier-Accumulator
DDR-FCRAM-II Low-Voltage Differential Signal LVDS Drivers/Receivers
grfpu_brief The GRFPU is an IEEE-754 compliant ?oating-point unit, supporting both single and double precision oper-ands. The advanced design combines high throughput with low latency, providing up to 250 MFLOPS on a 0.13 um ASIC process.
URFM-sps180 High Density Synchronous Single-Port Register File Compiler
QCPLL23-13T 50 to 700 MHz Phase-Locked Loop for digital clock synthesis using 1.0V/3.3V FSG process. In=12.5-43.75 MHz. Out= 50 - 700 MHz. Padring
CI3146ca 10-Bit, 30 MHz, 3.3V Pipeline ADC
FSA0A_C_SR UMC 0.18um Logic GII process standard synchronous high performance single port SRAM memory compiler.
SafeZone IP 2.0 - Mobile Security Engines Embedded security IP for mobile, entertainment and consumer devices.
CI8358nf 20-bit, 90dB Dynamic Range, 8 to 48kHz Sampling Frequency, Stereo Audio DAC
CB0040 Convolutional Encoder
FXREG020HB0A 3.3V with 100mA driving capability, Istb=65uA Linear Regulator; 0.15um Logic Std/HS process
MCS 51 Compatible 8-bit Microcontroller Core The Microcontroller Core is cycle compatible to the MCS 51 family of devices.
QCDLL6-13T 400 - 800 MHz DLL. 4 phase outputs 1 slave loop
Rambus?RDRAM?ASIC IO Cell (RAC) RDRAM: The industry s highest performance memory architecture in production
DES The DES Engine is a low power, low cost hardware co-processor, which implements the Data Encryption Standard (DES) algorithm. The Engine is compatible with the C*CORE Bus and performs both encryption and decryption. As a trade-off between size (cost) and
FG70A_L_T50_PCI_IO UMC 0.45um LOGIC process Gate Array Low Voltage true 5.0V PCI IO cells
IP Module Evaluation Tutorial IP modules are available for ispXPLD, ispXPGA, ORCA4 FPGA, ORCA FPSC, LatticeEC/ECP, and LatticeXP technologies. This tutorial is written to support all device technologies, with differences noted where important.
USB-OTG2 USB 2.0 (FS & HS) On-The-Go IP Core
hsca_adder Hierarchical Carry Save Algorithm (HCSA) is a modification of well known adder algorithm. Comes as VHDL IP core, shows good timing and small area requirements. The Generic HCSA ALU VHDL IP Core presents an example of HCSA methodology.
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