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IP Name(IP名称) IP Description(IP描述) IP Owner(IP提供商)
ISI-250 USB 2.0 Device Core
Data Side OCM Bus v1.0 The DSOCM_V10 core is a data-side On-Chip Memory (OCM) bus interconnect core. The core connects the PowerPC ? 405 data-side OCM interface to OCM peripherals, such as the data-side OCM BRAM controller (DSBRAM_IF_CNTRL). For information about the PowerP
TCI-U13SP-DSLPLL UMC L130SP 0.13um Deskew PLL - 59MHz-295MHz
PDKChek?/a> Independent die-level monitor
Artisan 0.18um PECL input receiver for TSMC
CW000024 USB 2.0 AHB Function
CW000564 GigaBlaze Top
M146818S Programmable Real Time Clock for SOC applications
Y8002 Microprocessor The Y8002 design is supplied in Verilog HDL format and can be implemented in any technology supported by a logic synthesis tool that accepts Verilog HDL.
GEOFIG Computer Arithmetic of Geometrical Figures
C56000 24-bit fixed-point Digital Signal Processor, core modeled after Motorola DSP56002
AU-NB8008 HPNA 2.0 AMBA Subsystem Core AU-NB8008 HPNA 2.0 AMBA Subsystem Core; 128 to 2048 byte Transmit FIFO ? 128 to 2048 byte Receive FIFO;
Programmable Amplifiers
Amphion CS5312 Pseudo-Random Number Generator
Artisan 0.18um PCI 66MHz I/O for TSMC
UV18210 Frequency Synthesizable PLL (Vcc=1.8V,Fin=5~50MHz, Fout=100~500MHz, Jitter= +/
I2C I2C Compatible Serial Interface
cclasic/gas/ultrarx/1.0 ultrasonics receiver (Gas sensor applications)
IPC-1001 Timer a programmable 16-bit counter/timer.
TCI-T18E-DSLPLL TSMC CL018E 0.18um Deskew PLL - 65MHz-325MHz
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